This invention pertains to computer circuits and, more particularly, to a logic circuit for placing a microprocessor in a hold state in response to a hold request signal, and for locking the microprocessor to the local central processing unit (CPU) bus for a predetermined minimum period of time.
The Intel family of microprocessors, including the 80286, 80386 and 80486, support a common interface to allow other devices access to the local CPU bus. These other devices are typically other processors, such as direct memory access (DMA) controllers, which require access to the local CPU bus.
The Intel microprocessor has a HOLD input pin for receiving a "hold request" from the device that requires access to the CPU bus. The processor responds to this request by releasing or "floating" the local CPU bus, to allow the requesting device temporary control of the bus. Upon releasing the bus, the microprocessor asserts its HOLDA ("Hold Acknowledge") pin active to notify the requesting device that the bus has been released. The microprocessor does not respond instantaneously when a hold request is asserted at the HOLD pin, but waits for the end of the current local bus cycle or the end of an "atomic" transfer. (An atomic transfer is a transfer of a predetermined number of bytes of code.) The HOLDA pin will remain in the active state until the requesting device removes the hold request from the HOLD pin. When HOLD goes inactive, the microprocessor will inactivate HOLDA and retake control on the local CPU bus.
Thus, the device requesting control of the local CPU bus must wait until the microprocessor completes its current bus cycle or atomic transfer. This period of time between the hold request and the time the microprocessor acknowledges that it has released the bus is known as "hold latency".
Typically, the longest hold latency period occurs when the hold request is asserted at the beginning of an atomic transfer. In the earlier generation of Intel processors, atomic transfers were only 2 or 4 bytes and hold latency was not a problem.
The 80486 processor, however, treats all memory code reads (code prefetches) as 16 byte atomic transfers. If the processor is executing code from an eight (8) bit device on the extended CPU bus, a latency period on the order of eight (8) microseconds may result (16 bytes.times.0.5 microseconds/byte=8 microseconds). This creates a problem in personal computer systems wherein a hold latency on the order of 8 microseconds has been known to create errors, such as diskette overruns, due to the length of time that the requesting device must wait for access to the local CPU bus.
Accordingly, the invention described below is an external (external to the microprocessor) logic circuit, suitable for use with an Intel 80486 or other microprocessor, that shortens the hold latency period inherent in the internal HOLD/HOLDA circuitry of the 80486 processor. The invention uses programmable array logic (PAL) to determine the current state of the microprocessor by monitoring the processor's I/O pins, and the PAL generates a signal (BCKOFF) in response to a hold request that places the microprocessor in an immediate hold state. The PAL also generates a hold acknowledge signal.
The invention also provides a "lockbus" feature that "locks" the microprocessor, when not idle, to the local CPU bus for a predetermined minimum period of time. This lockbus feature insures that the CPU has adequate access to the local CPU bus.